Diodes have many uses in many different types of electronic circuits. In many implementations, diodes consist of multiple layers of semiconductor material. Separate deposition steps form these multiple layers in a process that is not compatible with thin film transistor (TFT) processes. These diodes also have relatively high junction capacitance compared to the design rules for TFT processes. The relative thickness of these devices renders them unusable and incompatible with thin-film transistor (TFT) processes and devices.
An alternative configuration employs a lateral, or co-planar, configuration. In this configuration, an n-type material forms one of the source/drain contacts and a p-type material forms the other source/drain contact. They are separated by a co-planar channel region generally formed from an intrinsic or undoped semiconductor, typically referred to as an i-channel or i-region. The arrangement of materials forms a P-I-N (PIN) diode. These devices have much higher compatibility with TFT processes and would generally be useful in TFT circuits. U.S. Pat. No. 7,064,418 provides an example of these types of devices.
Issues arise with these types of PIN diodes. They generally are not compatible with certain materials, such as amorphous silicon. High-speed circuits that have fast turn on, low parasitic capacitance and low reverse bias leakage current requirements cannot generally use these types of devices because of their unsatisfactory performance in these areas.